In “Debugging the RV32M1-VEGA RISC-V with Eclipse and MCUXpresso IDE” I described how to build and debug applications for the VEGA RISC-V board. In this article I describe how to enable FreeRTOS for RISC-V, based on the latest FreeRTOS V10.2.0 release.
Tag Archives: RISC-V
Debugging the RV32M1-VEGA RISC-V with Eclipse and MCUXpresso IDE
The ARM Cortex cores are everywhere. I like (and use) them a lot. Don’t take me wrong: maybe ARM needs some competition? It is very refreshing to see that something new is getting a lot of attention: RISC-V!
Open Source RISC – Eclipse with RISC-V on the SiFive HiFive1 Board
Open Source software has been around for decades. But open source on hardware especially microcontroller is not much a reality these days. But there is something which might change this: RISC-V is a free and open RISC instruction set architecture and for me it has the potential to replace some of the proprietary architectures currently used. RISC-V is not new, but it gets more and more traction in Academia (no surprise).
I wanted to play with RISC-V for over a year, but finally a week ago I did one of these “hey, let’s buy that board” thing again. Sometimes these boards get on a pile to wait a few weeks or longer to get used, but that one I had to try out immediately :-).