Open Source RISC – Eclipse with RISC-V on the SiFive HiFive1 Board

Open Source software has been around for decades. But open source on hardware especially microcontroller is not much a reality these days. But there is something which might change this: RISC-V is a free and open RISC instruction set architecture and for me it has the potential to replace some of the proprietary architectures currently used. RISC-V is not new, but it gets more and more traction in Academia (no surprise).

I wanted to play with RISC-V for over a year, but finally a week ago I did one of these “hey, let’s buy that board” thing again. Sometimes these boards get on a pile to wait a few weeks or longer to get used, but that one I had to try out immediately :-).

SiFive HiFive1 Board

SiFive HiFive1 Board

So what would make that RISC-V interesting? Well, the instruction set and architecture is open source, so everyone could build it.

💡 Not everything is open source. The instruction set is open source, but not the actual implementation, the peripherals (UART, USB, …) or the microarchitecture implementing all the tiny steps behind the instructions. See https://news.ycombinator.com/item?id=17392461 for a discussion on this. I see an open source instruction set as a good thing, as there are no royalties to pay for using it. And open source can help prevent potential security issues, but for this an open microarchitecture would help: Spectre, Meltdown, and Foreshadow just be the most recent issue, and they are all caused by the microarchitecture implementation. But RISC-V is definitely driving more to be open source beyond the instruction set itself.

But more important: it is fast. About twice as fast as the ARM Cortex-M4F on the Teensy 3.6:

HiFive1 Board

The board costs $59 and I ordered it directly from the CrowdSupply web page. It is actually an older board and was available early 2017. It seems that newer boards are now green and not black. It features Arduino headers for adding expansion boards or easy access to the microcontroller pins.

The microcontroller uses an external QSPI FLASH memory (128 MBit). The FE310 has only 16 KByte SRAM on-chip. The board can both use 3.3V and 5V logic levels as it has level shifter added.

HiFive1 Board Components

HiFive1 Board Components

It uses an unusual FTDI UART/JTAG interface (that bit device on the board). I rather wish they would have added a normal SWD/JTAG header to the board, which would solve lots of issues with that FTDI way. For example there is SEGGER J-Link support for RISC-V I could use *if* the board would make the JTAG signals available.

Freedom Studio

SiFive provides the Eclipse based ‘Freedom Studio’ (https://www.sifive.com/products/tools/). I have used v20180122 (beta3) on Windows 10. Download the zip file and unzip it to a folder (I used C:\Eclipse\FreedomStudio). It includes the GNU MCU Eclipse plugins for SiFive.

About Freedom Studio

About Freedom Studio

Examples

SiFive has a few examples installed in FreedomStudio\SiFive\Examples which I can import into the Eclipse workspace (File > Import > Existing Projects > Archive).

SiFive Example Projects

SiFive Example Projects

Debug Drivers

The HiFive1 board uses a FTDI device as interface for JTAG to the microcontroller. But by default Windows (and other OS) assume the FTDI is a normal USB-to-Serial device, and not a JTAG debug device. There is a detailed description of the issue on GNU MCU Eclipse. When I tried to use the board the first time, I only had errors with OpenOCD:

OpenOCD Problem

OpenOCD Problem

Open On-Chip Debugger 0.10.0+dev-gdd0dd7f64e03-dirty (2018-01-09-17:24)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
adapter speed: 10000 kHz
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Error: libusb_open() failed with LIBUSB_ERROR_NOT_FOUND
Error: no device found
Error: unable to open ftdi device with vid 0403, pid 6010, description 'Dual RS232-HS', serial '*' at bus location '*'

Checking the devices in the Windows Device Manager showed this:

FTDI USB Serial ports

FTDI USB Serial ports

Running the HiFive1_Driver.exe in FreedomStudio\SiFive\Drivers and updating the drivers did not work, and I tried that several times. What eventually worked was:

  1. Reboot Windows
  2. Connect the board
  3. Run HiFive1_Drivers.exe
HiFive1 FTDI Drivers

HiFive1 FTDI Drivers

Running the installer again:

updated drivers

updated drivers

And now the drivers were properly installed:

Dual RS232-HS

Dual RS232-HS

Not sure what the problem was, maybe because I had to have the board connected while installing the drivers?

Eclipse!

Finally I was able to debug with Eclipse the HiFive1 board :-):

Finally Debugging the HiFive1 Board

Finally Debugging the HiFive1 Board

Summary

The HiFive1 board is rather expensive compared to other boards, and that FTDI bridge is ugly (and closed source): a normal SWD/JTAG header would be much more useful and would cost less. OpenOCD works, but it would be good to have more and better options. The really good thing is that the Freedom Studio is Eclipse based, or you can build a DIY IDE with all the components available, so no need for proprietary tools at all.

💡 SiFive has as well a ‘Linux capable‘ device. So I think we might hear from RISC-V architectures more and more. And in June 2018 SiFive announced two now cores for the lower end of computing

In a nutshell, I get better performance than the usual ARM cores and it is open source. And I think with RISC-V available more and more, it has the potential to change the industry. RISC-V is not the mass market yet, but I think this is going to change.

A next step for me would be to explore more the SDK and have FreeRTOS with my library working on that board :-).

Happy RISCing:-)

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2 thoughts on “Open Source RISC – Eclipse with RISC-V on the SiFive HiFive1 Board

  1. Cool article, thanks for sharing! I was thinking of trying out one of these boards myself.

    However, I think you are a bit confused about ISA, architecture, and microarchitecture. Microarchitecture,
    is the CPU implementation in hardware that implements the ISA. Architecture is the combination of both the ISA and microarchitecture. RISC V is just an open source ISA. SiFive chips have a closed source microarchitecture that inplements the open source RISC V ISA. Additionally, the Spectre, Metldown, etc… vulnerabilities occur at the microarchitecture level. That is why really old x86 chips without speculative execution don’t have these vulnerabilities. Thus, the RISC V ISA being open source has nothing to do with the potential for speculative execution vulnerabilities on SiFive chips.

    Like

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