The FRDM-KL25Z Open Source Logic Analyzer based on SUMP presented here was already very useful with the added trigger support. But it was not capable to do a sampling rate above a few hundred kHz. That’s ok for slower probing, but not for anything with a higher speed. Using DMA (Direct Memory Access) instead of timer based sampling can remove that limitation :-).
Thanks to the excellent work of Reiner Geiger, a higher data rate is now possible, up to 24 MHz :-).
❗ Above 4 MHz sampling rate, the timing shown in the OLS viewer seems to be off. E.g. at 4 MHz sampling rate the 1 kHz signal is shown as 2 kHz, 3 kHz at 12 MHz and 6 kHz at 24 MHz.
The project is implemented with CodeWarrior for MCU10.3. Three components are used for the DMA support:
- TimerUnit_LDD to generate a clock for DMA up to 24 MHz.
- Init_GPIO to configure an input pin to trigger a DMA transfer.
- Init_DMA to configure the DMA with channels, data source and pin settings.
The timer used creates a signal up to 24 MHz on pin PTD0:
This DMA clock is used as input signal to PTD2, which is configured to create a DMA transfer:
This means that pin PTD0 needs to be connected with PTD2, and will generate a clock from 10 kHz up to 24 MHz:
The DMA_Init component is configured to read from Port C and store the data into the 14 KByte Data buffer with auto-incrementing the address. The event
DMA1_OnComplete() is used to signal the firmware that the DMA transfer has been finished:
Note: There is a DMATransfer_LDD component available in Processor Expert. According to Reiner this one was not usable, as it was checking if the DMA has been released (which was not possible to disable). So he used the Init_DMA component instead, and saved with this as well 4 KByte of code.
The usage of the DMA is pretty self-explanatory in the source file Logic.c.
OSL LogicSniffer Client
The CodeWarrior project has a new the OLS Logic Sniffer (http://www.lxtreme.nl/ols/) configuration file (ols.profile-FRDM-KL25ZLogicLogger.cfg). Copy that file into the ‘plugins’ folder of the OLS client to update the existing one.
💡 If the updated client file is not recognized: deleting the ‘felix-cache’ subfolder can help.
‘Showing device metadata’ now should report V2.1:
The Acquisition tab shows now a sampling rate up to 24 MHz:
Now everything is set up to sample at high speed 🙂
With the usage of DMA, the FRDM-KL25Z logic analyzer is able to do sampling up to a rate of 24 MHz. With this, it is possible to sample even high-speed signals e.g. on an SPI bus :-). I’ll see if I can find the minor timing display problem above 4 MHz,which is not a big deal. In any case, DMA rocks :-).
Many thanks to Reiner for his DMA work!
The updated project is available on GitHub here.
Happy DMAing 🙂