ARM Cortex-M, Interrupts and FreeRTOS: Part 2

In “ARM Cortex-M, Interrupts and FreeRTOS: Part 1”  I started with the ARM Cortex-M interrupt system. Because the ARM implementation cann be very confusing, I confused myself and had to fix and extend the description in Part 1 :-). Thank for all the feedback and comments!

Originally I wanted to cover FreeRTOS in Part 2. Based on the questions and discussions in Part 1 I thought it might be a good idea to provide visual examples.

NXP KV58F ARM Cortex-M7

NXP KV58F ARM Cortex-M7

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ARM Cortex-M, Interrupts and FreeRTOS: Part 1

The ARM Cortex-M microcontroller are insanely popular. And it features a flexible and powerful nested vectored interrupt controller (NVIC). But for many, including myself, the Cortex-M interrupt system can be counter-intuitive, complex, inconsistent and confusing, leading to many bugs and lots of frustration :-(.

NXP KV58F ARM Cortex-M7

ARM Cortex-M7: NXP KV58

Understanding the NVIC and the ARM Cortex-M interrupt system is essential for every embedded application, but even for if using an realtime operating system: if you mess up with interrupts, very bad things will happen….

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